The present invention relates generally to semiconductor memory devices, and more particularly, to a novel data output buffer, suitable for use therein, characterized by reduced DC current levels and consequently, reduced noise levels.
In general, a data output buffer of a semiconductor memory device (e.g., a DRAM or SRAM) receives and amplifies data signals read out from a memory cell, and subsequently outputs the amplified data signals for utilization thereof externally of the semiconductor memory device. Such a data output buffer generally includes an output or final stage comprised of large-sized MOS transistors.
As semiconductor technology continues to evolve towards higher density and higher operational speed semiconductor memory devices, the noise generated by the data output buffers thereof has increased. This increase in the noise level of the data output buffers is largely attributable to the increase in the impulsive peak currents generated by the large-sized MOS transistors of the output stage thereof during transitions of the data signals from a logic low level to a logic high level and vice versa. In addition to undesirably increasing the noise level of the data output buffers, these impulsive peak currents adversely influence the power supply lines of the memory device, thereby degrading the performance and reliability of the memory device.
One recent proposal for minimizing the above-described impulsive peak currents is to limit the voltage swing of the output stage of the data output buffer. Conventionally, the output node of the output stage of the data output buffer is designed to swing fully between a reference voltage (Vss), which is typically 0.0V, i.e., ground, and the full power supply voltage (Vcc), which is typically 5.0V, upon transitions in the logic level of the data signal processed thereby.
More particularly, a data output buffer constructed in accordance with this recent proposal is disclosed in Japanese Patent Publication No. 1-149290, for an invention entitled "OUTPUT CIRCUIT OF STATIC RAM", and is depicted in FIG. 1. With reference now to FIG. 1, the output node N1 of the output stage OS of the data output buffer 10 depicted therein is designed to swing only between an intermediate level and the high level (Vcc), and between an intermediate level and the low level (Vss), thereby reducing the impulsive peak currents generated by the output stage OS upon transitions in the logic level of the data signals S,S'. As can be readily seen, the output stage OS is comprised of two relatively large-sized MOS transistors M1 and M2 connected in series between Vcc and Vss. The transistor M1 is a PMOS transistor, and the transistor M2 is an NMOS transistor. The output signal Dout of the data output buffer 10 is taken from output node N1 located intermediate the transistors M1 and M2. As will be more fully developed below, the data output buffer 10 includes a pull-down transistor m1, a pull-up transistor m2, and logic circuitry (1,2,3,4,5,6), which cooperatively function to maintain the voltage level of the data output signal Dout appearing at the output node N1 at the intermediate level prior to execution of a data output operation.
More particularly, with additional reference to the signal timing diagrams depicted in FIGS. 2A-2C,
on of the data output buffer 10 will now be described. In general, the data signals S,S' can have any one of three different logic states. In a first logic state, the data signal S is at the logic high level (i.e., high), and its complementary data signal S' is at the logic low level (i.e., low). In a second logic state, the data signal S is low, and the complementary data signal S' is high. In a third logic state, the data signals S,S' are both low.
In operation, when valid address signals (not shown) specifying a memory cell to be accessed are received, an address transition detection (ATD) circuit (not shown) of the memory device generates an ATD signal (not shown), which initiates a read operation, wherein data is read out of the specified memory cell. The read-out data appears as data signals S,S', which are input signals to the data output buffer 10. The data signals S,S' are in their third logic state (i.e., both low) after the ATD signal goes high and before the read-out data is received by the data output buffer 10, (i.e., before a data output operation is executed).
When the data signals S,S' are in their third logic state, the transistors M1 and M2 of the output stage OS are both turned off, because the data signal S is inverted by the inverter 1 before application thereof to the gate of the PMOS transistor M1, and the complementary data signal S' is twice-inverted by the series-connected inverters 5, 6 before application thereof to the gate of the NMOS transistor M2. Therefore, the signal presented to the gate of the PMOS transistor M1 is high, thereby turning this transistor off, and the signal presented to the gate of the NMOS transistor M2 is low, thereby turning this transistor off. A NAND gate 4 receives at one of its inputs the output signal Dout at one of its inputs the output signal Dout at one of its inputs, and an inverted version of the data signal S, via an inverter 3, at its outer input.
If the previous logic state of the output signal Dout was high, then the output of the NAND gate 4 goes low when the data signals S,S' are in their third logic state, because both inputs thereto will be high at this time. When this occurs, the low output of the NAND gate 4, which is applied to the gate of the pullup PMOS transistor m2, turns the transistor m2 on, thereby raising the level of the S'line connected to the gate of the NMOS transistor M2, and thus, partially turning on the transistor M2. In this connection, the channel sizes of the transistors m1 and m2 are selected such that when they are fully turned on, the transistors M1 and M2 are only slightly turned on. For example, when the transistor m2 is fully turned on, the voltage level of the S' line can be raised to 1/2 Vcc, rather than full Vcc, to thereby only partially turn on the transistor M2. When the transistor M2 of the output stage OS is partially turned on, the output signal Dout appearing at the output node N1 is decreased to its intermediate level. It should be noted that the output of the NOR gate 2 is low when the previous logic state of the output signal Dout was high, and thus, the NMOS transistor ml is turned off, thereby ensuring that the transistor M1 of the output stage OS stays turned off.
If the previous logic state of the output signal Dout was low, then the output of the NAND gate 4 goes high when the data signals S,S' are in their third logic state, since the Dout input to the NAND gate will be low at this time. When this occurs, the high output of the NAND gate 4, which is applied to the gate of the pull-up PMOS transistor m2, turns the transistor m2 off, thereby preventing the level of the S' line from being raised to a higher level, which keeps the NMOS transistor M2 of the output stage OS turned off. Further, when the previous logic state of the output signal Dout was low, the output of the NOR gate 2 goes high, since both inputs thereto will be low at this time. Consequently, the high output of the NOR gate 2 turns the pull-down NMOS transistor ml on, thereby lowering the voltage level of the signal line S, which partially turns on the PMOS transistor M1 of the output stage OS. When the transistor M1 is thus partially turned on, the output signal Dout appearing at the output node N1 is increased to its intermediate level.
Upon completion of a read operation, the data signals S,S' are driven to either their first or second logic state, depending upon whether a `1` or `0` was stored in the accessed memory cell. If the data signal S,S' are driven to their first logic state, the data signal S will be high and the complementary data signal S' will be low. In this case, the signal applied to the gate of the PMOS transistor M1 of the output stage OS, which is the inverse of the data signal S, will be low, thereby fully turning on the transistor M1, and thereby driving the output signal Dout from its intermediate level to its low level, i.e., the output node N1 will be pulled-up to its high level, Vcc. Further, if the data signals S,S' are driven to their second logic state, the data signal S will be low and the complementary data signal S' will be high. In this case, the signal applied to the gate of the NMOS transistor M2 of the output stage OS, which is the non-inverted complementary data signal S', will be high, thereby fully turning on the transistor M2, and thereby driving the output signal Dout from its intermediate level to its low level, i.e., the output node N1 will be pulled-down to its low level, Vss.
Thus, it can be appreciated that the output of the data output buffer 10 depicted in FIG. 1 is only drive between an intermediate level and a high level, or between an intermediate level and a low level, when a read operation is performed, and is maintained at o the intermediate level between successive read operations. Consequently, the impulsive peak currents generated by such a data output buffer are significantly reduced relative to conventional data output buffers, and thus, the noise generated during transition of the data signals is commensurately reduced. Further, the operational speed of such a data output buffer is significantly increased relative to conventional data output buffers. However, the data output buffer 10 still suffers from the following drawback. More particularly, in order to maintain the data output signal Dout at its intermediate level between successive read operations, it is necessary that the transistors M1 and M2 of the output stage OS thereof be slightly turned on, and further, that one of the transistors m1 of m2 be fully turned on, depending upon the previous logic state of the data output signal Dout. As such, DC current flows through both the transistors M1 and M2, as well as one of the transistors m1 or m2, during the period the data output signal Dout is maintained at its intermediate level, thereby generating undesirable noise. For example, when the data signals S,S' are in their third logic state (i.e., both low), and the previous data output signal Dout was high, the transistor m2 is turned on. When the transistor m2 is turned on, DC current will flow between the power supply voltage Vcc and the ground voltage Vss, via transistor mn2 of the inverter 6. Similarly, when the data signals S,S' are in their third logic state (i.e., both low), and the previous data output signal Dout was low, the transistor ml is turned on. When the transistor m2 is turned on, DC current will flow from the power supply voltage Vcc to the ground voltage Vss, via a PMOS transistor (not shown) of the inverter 1 and the source-drain channel of the transistor m1.
Thus, as is evident from the foregoing, there presently exists a need for a data output buffer for use in semiconductor memory devices which overcomes the above-described drawback of presently available data output buffers. The present invention fulfills this need.